What Do 400G, 800G, 1.6T, and 3.2T Actually Mean?

“400G”, “800G”, “1.6T”, and “3.2T” are the total data rate of an optical communications module — how much data one module moves as a whole, not the rate of a single wavelength or a single lane. The growth of AI training clusters has made these numbers industry buzzwords: a large GPU cluster holds tens of thousands of accelerators that must exchange gradients and parameters (collective communications such as all-reduce), and east-west traffic far exceeds the north-south traffic of traditional data centers — network bandwidth becomes the bottleneck for GPU utilization, and these numbers directly set the network cost and power budget of the whole AI cluster.

This article answers one question: what do 400G, 800G, 1.6T, and 3.2T actually mean? The answer: one formula (total rate = per-lane rate × lane count) plus two evolution axes (per-lane rate, lane count); each generation is a different combination of the two axes, and the bottleneck is shifting from optics to electronics.

(For the module’s internal architecture see “Optical Transceiver Module Architecture”; for laser types see “Optical Communication Laser Types”.)

1. One formula: total rate = per-lane rate × lane count

The total rate of every optical module can be written with one formula:

Total rate = per-lane rate × lane count

For example, 800G = 8 lanes × 100G per lane; 1.6T = 8 lanes × 200G. G is Gbit/s, T is Tbit/s (1.6T = 1600G, 3.2T = 3200G — T is just a unit conversion; the evolution logic is the same as G).

Learn this formula and you can “read” product names: 800G DR8 = 800G total, DR variant (500 m), 8 lanes (100G each); 1.6T DR8 = 8 lanes × 200G; 100G SR4 = 4 lanes × 25G @850 nm multimode 100 m. The same “800G” can be 8×100G or 16×50G — different lane configurations mean different cost and power.

Figure 1 | The two evolution axes: per-lane rate and lane count. Click for full size.

Evolution has two independent axes: per-lane rate (25G → 50G → 100G → 200G → 400G) and lane count (4 → 8 → 16). The two axes are independent, giving the industry flexibility: if per-lane can’t be pushed, add lanes; if the package’s pin count is limited, lower the per-lane rate. The cadence is roughly one generation every 2–3 years: 400G (2017) → 800G (2024) → 1.6T (in standardization).

2. Four standard generations: from 400G to 3.2T

400G (802.3bs, 2017) was the first T-class standard — before it, the data-center workhorse was the 100G module (802.3bm, 2014, 4 × 25G) — and the first to use PAM4 at scale (100G per lane = 53.125 GBd PAM4), with the 400GAUI-8 electrical interface (8 × 50G); three lane configurations for different reaches: 400GBASE-DR4 (4 lanes × 100G PAM4 @1310 nm, single-mode 500 m), 400GBASE-FR8/LR8 (8 wavelengths × 50G CWDM, 2 km / 10 km), and 400GBASE-SR16 (16 lanes × 25G @850 nm, multimode 100 m)^[1]. 400G arrived in 2017, exactly as hyperscale data centers were rising — one module moving 400G replaced “four 100G modules,” saving rack space, power, and cost, and it set the “double the total rate per module” evolution cadence. 400G remains a widespread configuration in storage and general-compute back-end networks today.

800G (802.3df, 2024) is the current volume workhorse: 800GBASE-DR8 (8 lanes × 100G PAM4 @1310 nm, 500 m) and DR8-2 (2 km), plus a 16 lanes × 50G configuration (the DR8+ family), in QSFP-DD or OSFP packages^[2]. 100G per lane maps to 112G SerDes, and the laser side is dominated by EMLs. In AI clusters, 800G serves both scale-out (between GPU clusters, between buildings) and scale-up (within the accelerator interconnect domain); each GPU’s network interface bandwidth doubles per generation (400G→800G→1.6T), and the optical modules follow.

1.6T (802.3dj, in standardization) centers on 200G per lane (212.5 GBd PAM4, mapping to 224G SerDes), with the 1.6TAUI-8 electrical interface (8 × 200G): 1.6TBASE-DR8 (8 lanes × 200G @1310 nm, 500 m)^[1]. It can also be built as 16 lanes × 100G (reusing 112G SerDes, a transitional option), but 8 × 200G is the mainstream direction — lane count unchanged, per-lane doubled, doubling the bandwidth demand on lasers and DSPs.

3.2T has no IEEE standard yet; it is an industry direction: 8 lanes × 400G (mapping to 448G SerDes, 425 GBd PAM4) or 16 lanes × 200G^[1]. OIF has held the 448Gbps Signaling for AI Workshop (2025) to push standardization^[4]. 3.2T packaging needs a new form factor (16 lanes, or 8 lanes at higher pin rates), still under MSA discussion. The two routes (8×400G vs 16×200G) are in an industry tug-of-war: the former demands higher pin rates, the latter eases electrical pressure but needs 16-lane packaging and more fiber.

3. Modulation and reach: PAM4 and DR/FR/LR/ZR

Early optical links used NRZ (Non-Return-to-Zero): each symbol carries 1 bit. PAM4 (4-level pulse amplitude modulation) carries 2 bits per symbol — the same symbol rate, double the rate; PAM4 became mainstream after 25G per lane^[3].

The price is a signal-to-noise-ratio (SNR) penalty: PAM4’s four level spacings are smaller than NRZ’s, so it is noise-sensitive and needs stronger FEC (forward error correction). PAM4 uses Gray-code mapping, so adjacent levels differ by only 1 bit and a single-bit error does not become a multi-bit error^[3]. The symbol rate being about 6.25% above the per-lane rate in the table (50G → 53.125 GBd) is the FEC overhead (1/0.9375 − 1 ≈ 6.25%). More levels (PAM6/PAM8) shrink the spacings further, raising the SNR penalty and power faster — PAM4 is the current balance point between power and rate. PAM4’s noise sensitivity also explains why the laser side is almost all EMLs after 100G per lane (see the laser-classification article); laser extinction ratio, TIA linearity, and DSP FEC capability all become key specifications for high-speed modules.

The same “400G” can be 500 m or 80 km — the distance variant is set by the suffix^[1]. The longer the reach, the more complex the modulation and detection: DR uses direct detection, ZR uses coherent detection:

The 8 CWDM wavelengths of FR/LR sit around 1295–1311 nm, each carrying one lane’s 50G. | ZR | 80 km | Single-wavelength coherent (DP-16QAM) |

ZR is special: IEEE’s 802.3cw project (400GBASE-ZR, single-wavelength coherent 80 km) was cancelled in 2024, and 400G ZR / 800G ZR moved to industry MSA efforts^[1]. The DR variant uses one fiber per lane (DR4 = 4, DR8 = 8), while ZR uses a single one — fiber count directly affects cabling cost, and patch-panel density doubles with the total rate. ZR’s DP-16QAM carries 4 bits per symbol, combined with coherent detection’s phase and amplitude demodulation. ZR compresses coherent technology into a pluggable module, making DCI (data-center interconnect) as simple as plugging in a network cable — a key step in coherent moving from long-haul into data centers.

4. The bottleneck: electronics, and the CPO alternative

Every doubling of per-lane rate doubles the SerDes (electrical interface) power and bandwidth demand — electrical signals travel a few centimeters of PCB from the ASIC to the module, the driver circuitry draws power, and loss rises with frequency. The SerDes generations (56G→112G→224G→448G) are the electrical industry’s cadence, and each generation needs a new CMOS process node behind it. A pluggable module’s power covers the lasers, DSP, and SerDes drivers — an 800G module typically draws more than 10 W, and 1.6T will be higher. The 3.2T bottleneck is electrical, not optical: 448G SerDes bandwidth, loss, and power all approach the current limits of CMOS^[4].

CPO (Co-packaged Optics) packages the optical engine (a miniaturized transceiver: lasers + photodetectors + driver circuitry) and the switch ASIC in the same package, drastically shortening the electrical path and eliminating the SerDes power of long PCB traces^[5]. CPO is developed mainly for large-scale data movement between AI accelerators; the price is maintainability — a failed pluggable means swapping a module (minutes), while a failed CPO means replacing the whole package (ASIC included, days), the key difference for data-center operations. So CPO lands first in high-power, high-density AI switch chips, while general data centers stay pluggable for the near term. Long term the two coexist: pluggables win on ecosystem and maintainability, CPO wins on power and density^[5].

Back to the opening question: 400G, 800G, 1.6T, and 3.2T are the total rate of an optical module, equal to per-lane rate × lane count; evolution advances along two axes (per-lane 25G→400G, lane count 4→16), with 400G (2017) and 800G (2024) standardized and 800G the volume workhorse, 1.6T in standardization, and 3.2T an industry direction. Scope: this article covers pluggable optical modules under Ethernet standards. Unresolved limits: every per-lane doubling doubles the bandwidth and power demand on lasers, TIAs, DSPs, and SerDes, and the electrical side is approaching CMOS limits — the maturity of CPO and 448G SerDes sets the pace of the next generation.